1. Field of the Invention
The invention relates to a semiconductor memory device, and particularly to a semiconductor memory device including a redundant column for repairing a defective memory cell column by replacement. More particularly, the invention relates to repairing of a defective column in the semiconductor memory device which has a plurality of memory blocks each having a redundant column and performs input/output of multi-bit data.
2. Description of the Background Art
Conventional semiconductor memory devices such as a static random access memory and a dynamic random access memory, which will be referred to as an "SRAM" and a "DRAM" hereinafter, respectively, includes redundant circuits for improving a product yield. If a defect is present in a memory portion (memory cell array) of a produced semiconductor memory device, this defective memory portion is repaired by the function of the redundant circuit. This redundant circuit usually includes a redundant row for repairing a row containing a defective memory cell in the memory cell array as well as a redundant column for repairing a column containing a defective memory cell. The defective row or column is replaced with a redundant row or column so that the defective memory cell is equivalently repaired.
FIG. 18 schematically shows a whole structure of a conventional SRAM. In FIG. 18, an SRAM 900 includes a plurality of memory blocks BK1-BKn each including a plurality of static memory cells arranged in rows and columns as well as a redundant column, and a block selector 1 for decoding a block address signal Z applied through an address buffer 4 to produce block select signals BS1-BSn for selecting one of memory blocks BK1-BKn. When the SRAM has a memory capacity of 4 Mbits, 64 memory blocks BK1-BK64 are included, and each memory block BK has a memory capacity of 64 Kbits. Data access (data write/read) is performed on a memory cell block selected by block selector 1.
SRAM 900 further includes an address buffer 2 to receive an externally applied row address signal RA for producing an internal row address signal X, an address buffer 3 to receive an externally applied column address signal for producing an internal column address signal Y, an address buffer 4 to receive an externally applied block address signal BA for producing an internal block address signal Z, input buffers 5a and 5b to receive input data DIa and DIb for producing internal write data on internal data line pairs DB1 and DB2, respectively, output buffers 6a and 6b to buffer internal read data DATA1 and DATA2 on internal data line pairs DB1 and DB2 for producing external read data DOa and DOb, respectively, and a read/write control circuit 7 responsive to an externally applied chip select signal /CS and an externally applied write enable signal /WE for producing an operation control signal WCON for buffers 5a, 5b, 6a and 6b to control write/read operations for a selected memory block.
SRAM 900 operates statically, and address buffers 2, 3 and 4 produce internal address signals X, Y and Z from address signals RA, CA and BA supplied thereto, respectively. When chip select signal /CS attains the active state at L-level, SRAM 900 is set to the selected state, and data access is performed. Writing or reading of data is executed depending on whether write enable signal /WE is at H-level or L-level.
Internal data line pairs DB1 and DB2 are provided commonly to memory blocks BK1-BKn, and access to data of 2 bits is performed on the selected memory block.
Each of memory blocks BK1-BKn includes one redundant column. For designating which of internal data line pairs DB1 and DB2 is to be connected to a redundant column, replacement IO program circuits RIP1-RIPn are provided for memory blocks BK1-BKn, respectively. Further, memory blocks BK1-BKn are provided with replacement column address program circuits RAP1-RAPn each for storing a defective column address designating a defective column to be repaired, respectively.
When block selector 1 generates a block select signal BSi (i=1-n) selecting a memory block BKi, a corresponding redundant column is selected in memory block BKi, and the redundant column is connected to one of internal data line pairs DB1 and DB2 in accordance with the information stored in replacement IO program circuit RIPi. Thus, a defective column in each memory block BK can be repaired independently of the other memory blocks.
FIG. 19 schematically shows a structure of memory blocks BK1-BKn shown in FIG. 18. Memory blocks BK1-BKn have the same structure, and FIG. 19 shows memory block BK1 as a representative.
In FIG. 19, memory block BK1 includes memory sub-blocks 910a and 910b provided corresponding to internal data line pairs DB1 and DB2, respectively, and a redundant column block 930 provided commonly to memory sub-blocks 910a and 910b. A row decoder 920 is provided commonly to memory sub-blocks 910a and 910b as well as redundant column block 930. Row decoder 920 is activated in response to activation of block select signal BS1 received from block selector 1 shown in FIG. 18, to decode internal row address signal X received from address buffer 2 shown in FIG. 18 and drive addressed rows in memory sub-blocks 910 and 910b as well as redundant column block 930 to the selected state.
Memory sub-block 910a includes a memory cell array 911a having a plurality of static memory cells arranged in rows and columns, bit line load circuits 912a arranged corresponding to the respective columns (bit line pairs) in memory cell array 911a for supplying a column current to corresponding bit line pairs, a column decoder 913a to decode an internal column address signal T received from address buffer 3 shown in FIG. 18 for producing a column select signal, multiplexers 914a provided corresponding to the respective columns in memory cell array 911a for connecting a selected column in memory cell array 911a to internal IO line pair I/Oa in accordance with the column select signal from column decoder 913a, a sense amplifier 916a selectively activated in response to write control signal WCON from read/write control circuit 7 and block select signal BS1, to amplify the internal read data on internal IO line pair I/Oa for transmission onto internal data line pair DB1, and a write buffer 915a selectively activated in response to block select signal BS1 and write control signal WCON, to amplify the data on internal data line pair DB1 for transmission onto internal IO line pair I/Oa.
Sense amplifier 916a and write buffer 915a are selectively activated in accordance with write control signal WCON when block select signal BS1 is active. When block select signal BS1 is inactive, sense amplifier 916a and write buffer 915 are set to an output high impedance state. Column decoder 913a executes the column selection in accordance with internal column address signal Y applied thereto.
Memory sub-block 910b has a structure similar to that of memory sub-block 910a, and includes a memory cell array 911b, a bit line load circuit 912b, a column decoder 913b, a multiplexer 914b, a sense amplifier 916b and a write buffer 915b. Sense amplifier 916b and write buffer 915b couple internal data line pair DB to internal IO line pair I/Ob when made active.
Redundant column block 930 has a redundant column 931 having the same rows as memory cell arrays 911a and 911b, a redundant column decoder 933 to generate a redundant column select signal in accordance with output signals of replacement column address program circuit RAP1 and replacement IO program circuit RIP1 while inhibiting the column selecting operation of column decoders 913a and 913b, a multiplexer (MUX) 934 to connect redundant column 931 to one of internal IO line pairs I/Oa and I/Ob in accordance with the select signal of redundant column decoder 933, and a bit line load circuit 932 to supply a column current to redundant column 931.
Replacement column address program circuit RAP1 receives internal column address signal Y and a stored defective column address, and activates redundant column decoder 933 when the internal column address signal designates a defective column address. When activated, redundant column decoder 933 produces the select signal for connecting redundant column 931 to the internal IO line pair corresponding to the internal data line pair designated by replacement IO program circuit RIP1.
Multiplexer 934 includes select gates for connecting redundant column 931 to internal IO line pairs I/Oa and I/Ob, respectively, and connects redundant column 931 to one of internal IO line pair I/Oa or I/Ob in accordance with the select signal received from redundant column decoder 933.
Memory cells in one column are connected to redundant column 931, so that a defective column in one of memory cell arrays 911a and 911b can be repaired by replacement in memory block BK1.
FIG. 20 schematically shows a structure of the memory sub-block. The memory sub-blocks included in memory blocks BK1-BKn have the same structure, and FIG. 20 shows a structure of memory sub-block 910a shown in FIG. 19.
In FIG. 20, memory cell array 911a includes a plurality of memory cells arranged in rows and columns. As a representative, FIG. 20 shows static memory cells 940a-940b arranged in two rows and two columns. Word lines L are arranged corresponding to the rows of memory cells, respectively, and bit line pairs BLP are arranged corresponding to the columns of memory cells, respectively. FIG. 20 shows two word lines WL0 and WL1 as well as two bit line pairs BLP0-BLP1 as a representative.
Word lines WL0 and WL1 are driven to the selected state in accordance with the row select signal applied from row decoder 920. Bit line pair BLP0 includes bit lines 941a and 941b transmitting complementary data signals, and bit line pair BLP1 includes bit lines 942a and 942b transmitting complementary data signals.
Bit line load circuit 912a includes N-channel MOS transistors 943a, 943b, 944a and 944b provided corresponding to bit lines 941a, 941b, 942a and 942b, respectively and operating in a diode mode. Each of MOS transistors 943a, 943b, 944a and 944b included in bit line load circuit 912a receives an array power supply voltage on its gate and a drain to precharge a corresponding bit line pair to a voltage level lower by its threshold voltage than the array power supply voltage. Further, each of the transistors 943a, 943b, 944a and 944b functions as a pull-up element in a data read operation, and supplies a current to the corresponding bit lines for causing a potential difference corresponding to the stored data of memory cell between the bit lines.
Internal IO line pair I/Oa includes internal IO lines 929a and 929b transmitting complementary data signals. These internal IO lines 929a and 929b are coupled to sense amplifier 916a and write buffer 915a.
Multiplexer 914a includes transfer gates 945a and 945b provided corresponding to bit lines 941a and 941b and turned on to couple bit lines 941a and 941b to internal IO lines 929a and 929b in response to a column select signal YS1a from column decoder 913a and transfer gates 946a and 946b provided corresponding to bit lines 942a and 942b and turned on to couple bit lines 942a and 942b to internal IO lines 929a and 929b in response to a column select signal YS2a from column decoder 913a.
Row decoder 920 is active when block select signal BS1 is active, to decode internal row address signal X to drive word line WL (WL0, WL1, . . . ) corresponding to an addressed row to the selected state. Column decoder Y is inactive and is inhibited of the column select operation when a redundant column select signal RCSa applied from redundant column decoder 933 shown in FIG. 19 is active. When redundant column select signal RCSa is inactive, column decoder 913a performs the decoding in accordance with internal column address signal Y, and drives one of column select signals YS1a, YS2a, . . . to the selected state.
In the data read operation, sense amplifier circuit 916a is activated. In the data write operation, write buffer 915a is activated. Therefore, when memory block BK1 shown in FIG. 19 is selected, data access via a bit line pair selected by column decoder 913a is performed if a defective column is not addressed and the data access to a selected memory cell is performed via output buffer 6a or input buffer 5a shown in FIG. 18. When the defective column of memory cell array 911a is addressed, redundant column select signal RCSa is activated, and column decoder 913a maintains the inactive state. A selected memory cell on redundant column 931 shown in FIG. 19 is coupled to internal IO line pair I/Oa (row decoder 920 selects a row even on the redundant column).
FIG. 21 shows a structure of the memory cell. The memory cell is a static memory cell. The normal memory cell and the redundant memory cell have the same structure. FIG. 20 shows, as a representative, the structure of memory cell 940a shown in FIG. 20. In FIG. 20, memory cell 940a includes an N-channel MOS transistor 948a turned on to couple bit line 941a to a storage node SNa in response to a signal potential on word line WL0, an N-channel MOS transistor 948b turned on to couple bit line 941a to a storage node SNa in response to a signal potential on word line WL0, an N-channel MOS transistor 947a connected between storage node SNa and the ground node and having a gate connected to storage node SNb, an N-channel MOS transistor 947b connected between storage node SNb and the ground node and having a gate connected to storage node SNa, a resistance element 949a of a high resistance connected between a power supply node and storage node SNa, and a resistance element 949b of a high resistance connected between the power supply node and the storage node SNb.
When memory cell 940a is selected, the signal potential on word line WL0 rises to H-level, and MOS transistors 948a and 948b are turned on to connect storage nodes SNa and SNb to bit lines 941a and 941b, respectively. The potentials on storage nodes SNa and SNb are latched by MOS transistors 947a and 947b. Bit lines 941a and 941b are supplied with currents from the bit line load circuit (MOS transistors 943a and 943b). The potentials on bit lines 941a and 941b depend on the currents supplied from corresponding bit line load transistors 943a and 943b, the channel resistances of accessing MOS transistors 948a and 948b, and the resistance values of MOS transistors 947a and 947b for storage. When data at H-level is held on storage node SNa, MOS transistor 947b is on, and MOS transistor 947a is off so that a current hardly flows from bit line 941a to storage node SNa. Meanwhile, a current flows from bit line 941b to the ground node via MOS transistors 948b and 947b, so that the potential on bit line 941b lowers. Thus, a potential difference occurs between bit lines 941a and 941b, and is amplified by the sense amplifier so that internal read data DATA1 is produced. In the write operation, bit lines 941a and 941b are set to the levels corresponding to the write data owing to the large current drive power of write buffer 915a, and the write data is transmitted to storage nodes SNa and SNb.
FIG. 22 shows another structure of the static memory cell. In this structure of the memory cell shown in FIG. 22, resistance elements 949a and 949b of a high resistance are replaced with P-channel MOS transistors 950a and 950b having gates connected to storage nodes SNb and SNa, respectively. Structures other than the above are the same as those shown in FIG. 21, and the corresponding portions bear the same reference numerals, respectively.
In the memory cell structure shown in FIG. 22, the memory cell is formed of an inverter latch so that a through-current of the memory cell during standby is reduced. For example, when storage node SNa is at H-level, MOS transistor 950b is off and cuts off the through-currents through the path of MOS transistors 950b and 947b. Further, storage node SNb is at L-level, and MOS transistor 947a is off to cut off the through-currents through the path of MOS transistors 950a and 947a. In the memory cell structure shown in FIG. 22, writing and reading of the data is performed similarly to those of the memory cell shown in FIG. 21.
FIG. 23 is a timing chart showing changes in internal signals during data reading of a memory cell. In FIG. 23, the abscissa gives time, and the ordinate gives the voltage (volt).
"ADi" indicates changes in input signal of row address buffer 2, column address buffer 3 and block address buffer 4. "ADo" indicates changes in output signal of row address buffer 2, column address buffer 3 and block address buffer 4. "WL0" indicates changes in potential on word line WL0 connected to memory cell 940a. "I/O" indicates changes in potential on internal IO line pairs 929a and 929b. "SA0" indicates changes in output voltage of sense amplifier 916a. "Do" indicates changes in output voltage of data output buffer 6a. Operations for data reading of the conventional semiconductor memory device shown in FIGS. 18 to 22 will now be briefly described with reference to a timing chart of FIG. 23.
At time t0, externally applied address signal ADi (row address signal RA, column address signal CA and block address signal BA) changes, and address buffers 2, 3 and 4 buffer the applied address signals so that internal address signal ADo changes at time t1. Address buffers 2, 3 and 4, of which operation power supply voltage is, e.g., 5 V, convert the voltage level of externally applied address signal ADi of an amplitude of 3 V, to produce internal address signal ADo at the CMOS level.
Row decoder 920 is activated in response to block select signal BS1, to decode internal row address signal X received from row address buffer 2, for driving word line WL0 corresponding to the addressed row to the selected state at time t2. When the voltage level on word line WL0 rises, MOS transistors 948a and 948b shown in FIGS. 21 and 22 are turned on to couple storage nodes SNa and SNb to bit lines 941a and 941b, respectively. In accordance with the stored data on storage nodes SNa and SNb, the column currents flow through bit lines 941a and 941b, and the potential difference occurs between bit lines 941a and 941b. Column decoder 913a (or 913b) performs the column selection to drive column select signal YS1a to the selected state at H-level so that transfer gates 945a and 945b shown in FIG. 20 are turned on. Thereby, bit lines 941a and 941b are coupled to internal IO lines 929a and 929b, and the potentials on internal IO line pair I/Oa change in accordance with the selected memory cell data.
At time t4, sense amplifier 916a is activated in accordance with the control signal WCON and block select signal BS1 applied from read/write control circuit 907. The activation timing of sense amplifier 916a (or 916b) depends on an address transition detection signal of an ATD circuit (now shown). As a result of the sense operation of sense amplifier 916a, the output data signal of sense amplifier 916a changes at time t4.
Read data DATA1 of sense amplifier 916a is transmitted to output buffer 6a shown in FIG. 18 via internal data line pair DB1. Under the control of read/write control circuit 7, data output buffer 6a is activated to amplify the data on internal data line pair DB1 to generate external read data DOa (Do) at time t5. At time t5, external read data corresponding to the selected memory cell data is output.
The description has been given on the data read operation for memory cell 940a in memory cell array 911a of memory sub-block 910a. However, memory cell select operations similar to the above are performed in the other sub-block 910b of memory block BK1, and data of a selected memory cell is read onto internal data line pair DB2. Therefore, data of 2 bits are simultaneously output. The foregoing operations are performed when selected memory cells are present on normal columns other than a defective column.
When a selected memory cell is present on a defective column, access to this defective column is not performed, and access to the redundant column is performed. A defective memory cell column address indicating the position of a defective memory cell column is programmed by selectively blowing off a link element(s) (not shown) arranged in replacement column address program circuit RAP1. The replacement internal data line pair is programmed by selectively blowing off a link element(s) arranged in replacement IO program circuit RIP1. Accordingly, when an access to the column containing a defective memory cell is requested, multiplexer 934 selectively connects redundant column 931 to one of internal IO line pairs I/Oa and I/Ob in accordance with the output of redundant column decoder 933, which in turn is shown in FIG. 19 and operates in accordance with the output signals of replacement column address program circuit RAP1 and replacement IO program circuit RIP1.
When a defective column is present in memory cell array 911a and is to be repaired by replacement with redundant column 931, internal data line pair DB1 is programmed in replacement IO program circuit RIP1, and the redundant column is connected to internal IO line pair I/Oa. At this time, column decoder 913a is maintained inactive, and data on redundant column 931a is read onto internal IO line pair I/Oa. Further, the data of a selected memory cell in memory cell array 911b is read onto internal IO line pair I/Ob. Even in this case, reading of data of 2 bits is likewise performed.
FIG. 24 schematically shows a structure of a peripheral circuit of the redundant column shown in FIG. 19. In FIG. 24, redundant column 931 includes redundant memory cells 980a and 980c arranged in a single column. Each of redundant memory cells 980a and 980c has the structure shown in FIG. 21 or 22. Word lines WL0 and WL1 are arranged for redundant memory cells 980a and 980c, respectively. Memory cells 980a and 980c are connected to bit lines 981a and 981b. Bit line load circuit 932 includes MOS transistors 983a and 983b provided corresponding to bit lines 981a and 981b, respectively. Each of MOS transistors 983a and 983b has a gate connected to the power supply node, and operates in the diode mode.
Multiplexer 934 includes transfer gates 985a and 985b turned on to connect bit lines 981a and 981b to internal IO lines 929a and 929b, respectively, when a redundant column select signal RCSa applied from redundant column decoder 933 is activated, and transfer gates 986a and 986b turned on to couple bit lines 981a and 981b to internal IO lines 989a and 989b, respectively, when a redundant column select signal RCSb applied from redundant column decoder 933 is activated.
Redundant column decoder 933 drives one of redundant column select signals RCSa and RCSb to the selected state in accordance with replacement IO select signals RISa and RISb received from the replacement IO program circuit as well as a redundant column access instructing signal RYA received from the replacement column address program circuit. When one of redundant column select signals RCSa and RCSb is driven to the selected state, column decoders 913a and 913b shown in FIG. 19 are kept inactive.
The replacement column address program circuit stores a defective column address with a fuse programming, and drives a defective column replacement instructing signal RYA to the active state when an applied internal column address signal matches with the programmed defective column address. Redundant column decoder 933 drives one of redundant column select signals RCSa and RCSb to the selected state in accordance with replacement IO instructing signals RISa and RISb when redundant column access instructing signal RYA is activated. In the case where one redundant column is provided for two memory cell arrays, the redundant column can be connected to one of internal IO line pairs I/Oa and I/Ob depending on the memory cell array containing a defective column, and the repairing by replacement of the defective column can be performed.
The redundant column is provided in each of memory blocks BK1-BKn, and the replacement column address program circuit and the replacement IO program circuit are likewise provided for each of memory blocks BK1-BKn. Accordingly, repairing of a defective column in each memory block can be performed independently of the other memory blocks.
The replacement column address program circuit includes program circuits provided corresponding to respective bits Y&lt;i&gt; of the column address signal, respectively. These program circuits include fuse program circuits, and equivalently generates signals each indicating whether the programmed address bit matches with an applied column address signal bit. When all the output signals applied from the address program circuits provided corresponding to respective column address signal bits represent matching, redundant column access instructing signal RYA is driven to the active state. In the semiconductor memory device of a large storage capacity, therefore, the scale of the replacement column address program circuit increases as the bits of column address signal increase in number. In the case where the replacement column address program circuits are provided corresponding to memory blocks BK1-BKn, respectively, such a problem arises that the chip area increases. In particular, the fuse program circuit includes fuse elements, and occupies a large area. Therefore, the circuits for the redundant column programming occupy a large area, and the semiconductor memory device having a high integration density cannot be achieved.
In recent years, I/O bits of data of a semiconductor memory device have been increased, e.g., to 16 bits or 32 bits, and the number of internal data line pairs increases in accordance with this increase in number of the data bits. The replacement IO program circuit likewise includes fuse program circuits provided corresponding to the respective data bits. Further, these defective column address bits and the internal data line pairs (IO) must be programmed for each of memory blocks, and the programming is performed by blowing the link element(s) (fuse element(s)). For these reasons, the time required for programming for the defective column repairing increases, and the production efficiency lowers.
For overcoming the above problems, a structure shown in FIG. 25 has been proposed. In FIG. 25, replacement column address program circuit RAP and replacement IO program circuit RIP are provided commonly to memory blocks BK1-BKn. Structures other than the above are the same as those shown in FIG. 18. The structure shown in FIG. 25 uses only one replacement column address program circuit RAP and only one replacement IO program circuit RIP, and can reduce the area occupied by the circuits provided for repairing a defective column address. Further, the programming of the defective column address and the replacement IO is performed for only one circuit, and the programming of defective column address for each of memory blocks BK1-BKn is not required so that the time required for programming for the defective column repairing can be reduced, and the production efficiency can be improved.
In the structure shown in FIG. 25, however, only the same column address is repaired in memory blocks BK1-BKn by each respective redundant column. Therefore, defective columns can be repaired with corresponding redundant columns in all memory blocks BK1-BKn if defective columns are present at the same column address in respective memory blocks BK1-BKn. However, programming of the defective column address cannot be performed for the respective memory blocks BK1-BKn. This significantly reduces the flexibility in programming of a defective column address and the defective column repairing efficiency. Although the redundant column is provided in each of memory blocks BK1-BKn, the above structure is equivalent to the structure in which a single redundant column is provided commonly for memory blocks BK1-BKn, resulting in a low efficiency of use of the redundant columns. The replacement with a redundant column is likewise performed even in a memory block containing no defective column, and thus unnecessary replacement of the redundant column is performed.
The structure for repairing a redundant column is not restricted to the SRAM, and may be employed in other memories such as DRAMs and flash memories. These DRAMs and flash memories suffer from similar problems when input/output of multi-bit data is performed and a redundant column is to be repaired independently in each block.